View LC877816A_1168777.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENA0635
LC877816A
Overview
CMOS IC 16KB-byte and 512-byte RAM
8-bit 1-chip Microcontroller
The LC877816A is an 8-bit single chip microcontroller with the following on-chip functional blocks: * CPU: operable at a minimum bus cycle time of 250ns * ROM: 16 Kbytes * RAM: 512 x 9 bits * LCD controller/driver * 16bit timer x 2ch + 8bit timer x 1ch or more * Synchronous serial I/O port (with automatic block transmit/receive function) * Asynchronous/synchronous serial I/O port * System clock divider * 8-bit AD converter x 9-channel * 17-source 10-vectored interrupt system * Power save mode All of the above functions are fabricated on a single chip.
Features
ROM * 16384 x 8 bits RAM * 512 x 9 bits Minimum Bus Cycle Time * 250ns (4MHz) Note: The bus cycle time indicates ROM read time. Minimum Instruction Cycle Time (tCYC) * 750ns (4MHz)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.1.00
51607HKIM 20061017-S00010 No.A0635-1/21
LC877816A
Power Save Mode * Power save mode is available, when system clock is RC oscillation or crystal oscillation. Ports * Input/output ports Data direction programmable for each bit individually: 12 (P1n, P70 to P73) Data direction programmable in nibble units: 8 (P0n) (When N-channel open drain output is selected, data can be input in bit units.) * LCD ports Segment output: 24 (S00 to S23) Common output: 4 (COM0 to COM3) Bias terminals for LCD driver 5 (V1 to V3, CUP1, CUP2) Other functions Input/output ports: 8(PCn) * Oscillator pins: 4 (CF1, CF2, XT2, XT1) * Reset pin: 1 (RES) * Power supply: 4 (VSS1 to 2, VDD1 to 2) 1 (VDC) LCD Controller * Seven display modes are available. * Segment output (S16 to S23) can be switched to general purpose input/output ports. * Duty: 1/3duty, 1/4duty * Bias: 1/2bias, 1/3bias * LCD power 1) 1/3bias V1: 1.2V to 1.8V V2: 2.4V to 3.6V V3: 3.6V to 5.4V 2) 1/2bias V1: 1.2V to 1.8V V2: 2.4V to 3.6V V3: 2.4V to 3.6V (connect V2 and V3) Timers * Timer 0: 16 bit timer/counter with capture register Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register Mode 3: 16 bit counter with 16 bit capture register * Timer 1: PWM/16 bit timer/counter with toggle output function Mode 0: 2 channel 8 bit timer/counter (with toggle output) Mode 1: 2 channel 8 bit PWM Mode 2: 16 bit timer/counter (with toggle output) Toggle output from lower 8 bits is also possible. Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM. * Timer 4: 8-bit timer with 6-bit prescaler * Timer 5: 8-bit timer with 6-bit prescaler * Timer 6: 8-bit timer with 6-bit prescaler (with toggle output) * Timer 7: 8-bit timer with 6-bit prescaler (with toggle output) * Base Timer 1) The clock signal can be selected from any of the following : Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0 2) Interrupts of five different time intervals are possible.
No.A0635-2/21
LC877816A
SIO * SIO0: 8 bit synchronous serial interface 1) LSB first/MSB first is selectable 2) Internal 8 bit baud-rate generator (fastest clock period 4/3 tCYC) 3) Consecutive automatic data communication (1 to 256 bits) * SIO1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8 bit serial I/O (2-wire or 3-wire, transmit clock 2 to 512 tCYC) Mode 1: Asynchronous serial I/O (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC) Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC) Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection) AD Converter: * 8 bits x 9 Channels Remote Control Receiver Circuit (connected to P73/INT3/T0IN terminal) * Noise rejection function (noise rejection filter's time constant can be selected from 1/32/128 tCYC) Watchdog Timer * Watchdog timer can produce interrupt or system reset. * Watchdog timer has two types. 1) Use an external RC circuit 2) Use the microcontroller's base timer Interrupts * 17 sources, 10 vectors 1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or lower priority interrupt request is postponed. 2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. In the case of equal priority levels, the vector with the lowest address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L INT3/Base timer T0H T1L/T1H SIO0 SIO1 ADC/T6/T7 Port 0/T4/T5 Interrupt Source
* Priority levels X > H > L * For equal priority levels, vector with lowest address takes precedence. Subroutine Stack Levels * 256 levels maximum (the stack is allocated in RAM) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * On-chip RC oscillation for system clock use. * CF oscillation (4MHz) for system clock use. (Rf built in) * Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in)
No.A0635-3/21
LC877816A
System Clock Divider Function * Low power consumption operation is available * Minimum instruction cycle time (0.75s, 1.5s, 3s, 6s, 12s, 24s, 48s, 96s, 192s can be switched by program (when using 4MHz main clock) Standby Function * HALT mode: HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.) 1) Oscillation circuits are not stopped automatically. 2) Released by the system reset or interrupts. * HOLD mode: HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped. 1) CF, RC and crystal oscillation circuits stop automatically. 2) Released by any of the following conditions. (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2 (3) Port 0 interrupt * X'tal HOLD mode: X'tal HOLD mode is used to reduce power consumption. Program execution is stopped. All peripheral circuits except the base timer are stopped. 1) CF and RC oscillation circuits stop automatically. 2) Crystal oscillator operation is kept in its state at HOLD mode inception. 3) Released by any of the following conditions (1) Low level input to the reset pin (2) Specified level input to one of INT0, INT1, INT2 (3) Port 0 interrupt (4) Base-timer interrupt Debugger * On chip debugger (LC87F7032A) LC87F7032A and LC877816A differ in following points. When LC87F7032A is power save mode, Current consumption doesn't decrease. When LC87F7032A is power save mode, X'tal voltage level doesn't change. LC87F7032A has P2 registers (P2, P2DDR). But, LC877816A doesn't have them. Package Form * QFP64J(7x7): Lead-free type * QIP64E(14x14): Lead-free type
No.A0635-4/21
LC877816A
Package Dimensions
unit : mm (typ) 3289
9.0 7.0 48 49 33 32
7.0
64 1 0.4 (0.5) 0.16 16
17 0.125
1.2max
0.1
(1.0)
SANYO : TQFP64J(7X7)
Package
unit : mm (typ) 3159A
17.2 14.0 48 49 33 32
9.0
14.0
64 1 0.8 (1.0)
(2.7)
17 16 0.35 0.15
3.0max
0.1
SANYO : QIP64E(14X14)
17.2
0.8
0.5
No.A0635-5/21
LC877816A
Pin Assignment
S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0
S15
S14
S13
S12
S11
S10
S09
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RES XT1 XT2 VSS1 CF1 CF2 VDD1 P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/CKO/DBGP0 P06/T6O/DBGP1 P07/T7O/DBGP2 NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 P70/INT0/T0LCP/AN5 2 P71/INT1/T0HCP/AN6 3 P72/INT2/T0IN/AN7 4 P73/INT3/T0IN/AN8 5 VDD2 6 VSS2 7 P10/SO0 8 P11/SI0/SB0 9 P12/SCK0 10 11 12 13 14 15 16 P14/SI1/SB1 P15/SCK1 P17/T1PWMH P16/T1PWML P13/SO1 CUP1 CUP2 32 31 30 29 28 27 26 S07 S06 S05 S04 S03 S02 S01 S00 COM3 COM2 COM1 COM0 V3 V2 V1 VDC
S08 25 24 23 22 21 20 19 18 17
LC877816A
Top view
SANYO: TQFP64J(7x7) SANYO: QIP64E(14x14)
"Lead-free Type" "Lead-free Type"
No.A0635-6/21
LC877816A
System Block Diagram
Interrupt control
IR
PLA
Standby control
Clock generator
CF RC
ROM
X'tal
PC SIO0 Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B Register
Timer 1
Port 7
C Register
Timer 4
ADC ALU
Timer 5
Timer 6
PSW INT0 to 3 Noise rejection filter
Timer 7
RAR
Base timer RAM LCD controller Stack pointer
Watchdog timer
No.A0635-7/21
LC877816A
Pin Description
Pin name VSS1, VSS2 VDD1, VDD2 VDC CUP1, CUP2 PORT0 P00 to P07 I/O I/O - Power supply + Power supply + Power supply * Capacitor connecting terminals for step-up/step-down * 8bit input/output port * Data direction programmable in nibble units * Use of pull-up resistor can be specified in nibble units * Input for HOLD release * Input for port 0 interrupt * Other pin functions Input for ADC channel (AN0 to AN4) P05: Clock output (system clock/subclock) When it's LC87F7032A, P05 uses as DBGP0. P06: Timer 6 toggle output When it's LC87F7032A, P06 uses as DBGP1. P07: Timer 7 toggle output When it's LC87F7032A, P07 uses as DBGP2. PORT1 P10 to P17 I/O * 8bit input/output port * Data direction programmable for each bit * Use of pull-up resistor can be specified for each bit individually * Other pin functions P10: SIO0 data output P11: SIO0 data input or bus input/output P12: SIO0 clock input/output P13: IO1 data output P14: SIO1 data input or bus input/output P15: SIO1 clock input/output P16: Timer 1 PWML output P17: Timer 1 PWMH output/Buzzer output PORT7 P70 to P73 I/O * 4bit Input/output port * Data direction can be specified for each bit * Use of pull-up resistor can be specified for each bit individually * Other functions P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer/AN5 P71: INT1 input/HOLD release input/Timer0H capture input/AN6 P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/AN7 P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer0H capture input/AN8 Input for ADC channel (AN5 to AN8) * Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Yes Function Option No No No No Yes
S0 to S15 S16/PC0 to S23/PC7 COM0 to COM3 V1 to V3 RES XT1 XT2 CF1 CF2
O I/O O I/O I I I/O I O
* Segment output for LCD * Segment output for LCD * Can be used as general purpose input/output port (PC) * Common output for LCD * LCD output bias power supply * Capacitor connecting terminals for step-up/step-down * Reset terminal * Input for 32.768kHz crystal oscillation * When not in use, connect to VDD2 * Output for 32.768kHz crystal oscillation * When not in use, set to oscillation mode and leave open * Input terminal for ceramic oscillator * When not in use, connect to VDD2 * Output terminal for ceramic oscillator * When not in use, leave open
No No No No No No No No No
No.A0635-8/21
LC877816A
Port Output Types
Port form and pull-up resistor options are shown in the following table. Port status can be read even when port is set to output mode.
Port Name P00 to P07 Option selected in units of 1 bit Option type 1 2 P10 to P17 1 bit 1 2 P70 P71 to P73 S16(PC0) to S23(PC7) No No 1 2 3 CMOS Nch-open drain CMOS Nch-open drain Nch-open drain CMOS CMOS, Pch-Open Drain Nch-Open Drain Output type Pull-up resistor Programmable(Note 1) No Programmable Programmable Programmable Programmable No
Note 1: Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00 to 03, P04 to 07). *1: Connect as follows to reduce noise on VDD. VSS1 and VSS2 must be connected together and grounded.
LSI VDD1 Power supply VDD2 V1 V2 V3 VDC CUP1 CUP2
Back up capacitors *2
VSS1 VSS2
*2: The power supply for the internal memory is VDC. VDD1 and VDD2 are used as the power supply for ports. When VDD1 and VDD2 are not backed up, the port level does not become "H" even if the port latch is in the "H" level. Therefore, when VDD1 and VDD2 are not backed up and the port latch is "H" level, the port level is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from VDD to GND in the input buffer. If VDD1 and VDD2 are not backed up, output "L" by the program or pull the port to "L" by the external circuit in the HOLD mode so that the port level becomes "L" level and unnecessary current consumption is prevented.
No.A0635-9/21
LC877816A
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = 0V
Parameter Supply voltage Supply voltage For LCD Symbol VDD max VLCD Pins/Remarks VDD1, VDD2, V2 V1, V2 V3 Input voltage Input/Output voltage Peak output High level output current current VI VIO(1) IOPH(1) XT1, CF1, RES * Port0, 1, 7 * PortC Ports 0, 1, 7, C * CMOS output selected * Current at each pin -4 Conditions VDD[V] VDD1=VDD2=V2 min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Specification typ max +4.3 1/2 VDD VDD 3/2 VDD VDD+0.3 VDD+0.3 V unit
Total output current
IOAH(1) IOAH(2) IOAH(3) IOAH(4)
Port 7 Port 0 Port 1 Port C Ports 02 to 07 Port 1, 7, C Port 00, 01 Port 7 Port 0 Port 1 Port C TQFP64J(7x7) QIP64E(14x14)
Total of all pins Total of all pins Total of all pins Total of all pins Current at each pin Current at each pin Total of all pins Total of all pins Total of all pins Total of all pins Ta=-30 to+70C
-10 -25 -25 -15 6 15 10 35 25 15 200 420 -30 -55 +70 C +125 mW mA
Low level output current
Peak output current
IOPL(1) IOPL(2)
Total output current
IOAL(1) IOAL(2) IOAL(3) IOAL(4) Pd max
Allowable power dissipation Operating ambient temperature Storage ambient temperature
Topr Tstg
No.A0635-10/21
LC877816A
Allowable Operating Conditions at Ta = -30C to +70C, VSS1 = VSS2 = 0V
Parameter Operating supply voltage range Symbol VDD(1) VDD(2) VDD(3) VDD(4) Supply voltage range in Hold mode Input high voltage VIH(2) VIH(3) VIH(4) Input low Voltage VIL(2) VIL(3) VIL(4) Operation cycle time External system clock frequency Oscillation frequency range (Note 2-1) FmRC FsX'tal XT1, XT2 FmCF CF1, CF2 FEXCF(1) CF1 * CF2 open * system clock divider:1/1 * external clock DUTY=50 5% 4MHz ceramic resonator oscillation See fig. 1 RC oscillation VDD=3.0V, Ta=25C 32.768kHz crystal resonator oscillation See fig. 2 2.4 to 3.6 32.768 kHz 2.4 to 3.6 300 500 700 kHz 2.4 to 3.6 4 MHz 2.4 to 3.6 0.1 4 tCYC 2.4 to 3.6 VIL(1) VIH(1) * Ports 1, 71 to 73 * Port 70 input/interrupt * Ports 0, C Port 70 Watchdog timer XT1, CF1, RES * Ports 1, 71 to 73 * Port 70 input/interrupt * Ports 0, C Port 70 Watchdog timer XT1, CF1, RES Output disable Output disable 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 VSS VSS VSS 2.25 4.28 0.2VDD 0.8VDD -1.0 0.25VDD 200 200 s MHz Output disable 2.4 to 3.6 VSS 0.2VDD Output disable Output disable 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 Output disable 2.4 to 3.6 0.3VDD +0.7 0.3VDD +0.7 0.9VDD 0.75VDD VDD VHD Pins/Remarks VDD1=VDD2=V2 Normal mode VDD1=VDD2=V2 Power save mode VDD1=VDD2=V2 Conditions VDD 0.37stCYC200s 0.75stCYC200s 2.25stCYC200s 4.28stCYC200s Keep RAM and register data in HOLD mode. 2.2 3.6 min 3.0 2.4 3.0 2.4 Specification typ max 3.6 3.6 3.6 3.6 unit
VDD VDD VDD
V
Note 2-1: The parts value of oscillation circuit is shown in table 1 and table 2.
No.A0635-11/21
LC877816A
Electrical Characteristics at Ta = -30C to +70C, VSS1 = VSS2 = 0V
Parameter High level input current Symbol IIH(1) Pins/Remarks * Ports 0, 1, 7 * Port C * RES Conditions VDD[V] * Output disabled * Pull-up resister OFF. * VIN=VDD (including OFF state leak current of the output Tr.) IIH(2) IIH(3) Low level input current IIL(1) XT1, XT2 CF1 * Ports 0, 1, 7 * Port C * RES When configured as an input port VIN=VDD VIN=VDD * Output disabled * Pull-up resister OFF. * VIN=VSS (including OFF state leak current of the output Tr.) IIL(2) IIL(3) High level output voltage VOH(2) Low level output voltage VOL(2) P00, P01 VOL(1) VOH(1) XT1, XT2 CF1 Ports 0, 1, 7 CMOS output option Port C Ports 0, 1, 7 IOH=-0.1mA IOL=1.6mA IOL=0.8mA IOL=5.0mA IOL=2.5mA VOL(3) LCD output voltage regulation VODLC COM0 to COM3 VODLS Port C S0 to S23 IOL=0.1mA IO=0mA V1, V2, V3 LCD level output IO=0mA V1, V2, V3 LCD level output Resistance of pull-up MOS Tr. Hysterisis voltage Pin capacitance CP VHYS(1) * Ports 1, 7 * RES All pins * All Other Terminals Connected To VSS. * F=4MHz * Ta=25C 2.4 to 3.6 10 pF 2.4 to 3.6 0.1 xVDD V Rpu * Ports 0, 1, 7 VOH=0.9VDD 2.4 to 3.6 25 50 200 k 2.4 to 3.6 0 0.2 When configured as an input port VIN=VSS VIN=VSS IOH=-0.4mA IOH=-0.2mA 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 2.4 to 3.6 2.4 to 3.6 0 -1 -8 VDD-0.4 VDD-0.4 VDD-0.4 0.4 0.4 0.4 0.4 0.4 0.2 V 2.4 to 3.6 -1 2.4 to 3.6 2.4 to 3.6 1 8 A 2.4 to 3.6 1 min Specification typ max unit
No.A0635-12/21
LC877816A
Serial I/O Characteristics at Ta = -30C to +70C, VSS1 = VSS2 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/reception mode Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.4 to 3.6 Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) tdD0(3) * (Note 4-1-3) 2.4 to 3.6 (1/3)tCYC +0.15 2.4 to 3.6 2.4 to 3.6 0.03 2.4 to 3.6 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.4 to 3.6 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.4 to 3.6 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD See Fig. 6. min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 1tCYC +0.05 s
Serial output
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
Output clock
No.A0635-13/21
LC877816A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.4 to 3.6 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.4 to 3.6 (1/3)tCYC +0.05 0.03 2.4 to 3.6 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 2.4 to 3.6 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) Conditions VDD See Fig. 6. min 2 2.4 to 3.6 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Serial clock
s
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -30C to +70C, VSS1 = VSS2 = 0V
Parameter High/low level pulse width tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(6) Symbol tPIH(1) tPIL(1) Pins INT0(P70), INT1(P71), INT2(P72) INT3(P73) (Noise rejection ratio is 1/1.) INT3(P73) (Noise rejection ratio is 1/32.) INT3(P73) (Noise rejection ratio is 1/128.) RES Conditions VDD[V] * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that interrupt is accepted * Condition that event input to timer 0 is accepted * Condition that reset is accepted 2.4 to 3.6 200 s 2.4 to 3.6 256 2.4 to 3.6 64 2.4 to 3.6 2 tCYC 2.4 to 3.6 1 min Specification typ max unit
No.A0635-14/21
LC877816A
AD Converter Characteristics at Ta = -30C to +70C, VSS1 = VSS2 = 0V
Parameter Resolution Absolute accuracy Conversion time tCAD N ET Symbol Pin/Remarks AN0(P00) to AN4(P04), AN5(P70) to AN8(P73) AD conversion time=32xtCYC (ADCR2=0) (Note 6-2) Normal mode 2.4 to 3.6 AD conversion time=32xtCYC (ADCR2=0) (Note6-2) Power save mode AD conversion time=64xtCYC (When ADCR2=1) (Note 6-2) Normal mode 2.4 to 3.6 AD conversion time=32xtCYC (ADCR2=0) (Note6-2) Power save mode Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS -1 VAIN 2.4 to 3.6 3.0 to 3.6 2.4 to 3.6 3.0 to 3.6 22.4 (tCYC= 0.70s) 128 (tCYC= 4.00s) 128 (tCYC= 4.00s) 44.8 (tCYC= 0.70s) 256 (tCYC= 4.00s) 256 (tCYC= 4.00s) VSS (Note 6-1) Conditions VDD[V] min Specification typ 8 1.5 640 (tCYC= 20s) 640 (tCYC= 20s) 640 (tCYC= 20s) 1280 (tCYC= 20s) 1280 (tCYC= 20s) 1280 (tCYC= 20s) VDD 1 V A s max unit bit LSB
Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0635-15/21
LC877816A
Consumption Current Characteristics at Ta = -30C to +70C, VSS1 = VSS2 = 0V
Parameter Current consumption during normal operation (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pins/ Remarks VDD1= VDD2= V2 Conditions VDD[V] * FmCF=4MHz Ceramic resonator oscillation * FsX'tal=32.768kHz crystal oscillation * System clock: CF 4MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 * Normal mode * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 * Normal mode IDDOP(3) * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 * Power save mode IDDOP(4) * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/2 * Power save mode IDDOP(5) * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/1 * Normal mode IDDOP(6) * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/1 * Power save mode IDDOP(7) * FmCF=0Hz (No oscillation) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/2 * Power save mode Current consumption during HALT mode (Note 7-1) IDDHALT(1) HALT mode * FmCF=4MHz Ceramic resonator oscillation * FsX'tal=32.768kHz crystal oscillation * System clock: CF 4MHz oscillation * Internal RC oscillation stopped. * Divider: 1/1 * Normal mode IDDHALT(2) HALT mode * FmCF=0H (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 * Normal mode IDDHALT(3) HALT mode * FmCF=0H (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/1 * Power save mode 2.4 to 3.6 35 150 2.4 to 3.6 50 300 2.4 to 3.6 460 1600 2.4 to 3.6 1.5 15 2.4 to 3.6 2.5 17 A 2.4 to 3.6 15 60 2.4 to 3.6 40 180 2.4 to 3.6 50 225 2.4 to 3.6 150 600 2.4 to 3.6 1100 3200 min Specification typ max unit
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A0635-16/21
LC877816A
Continued from preceding page.
Parameter Current consumption during HALT mode (Note 7-1) IDDHALT(5) Symbol IDDHALT(4) Pins/ Remarks VDD1= VDD2= V2 HALT mode * FmCF=0H (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: RC oscillation * Divider: 1/2 * Power save mode HALT mode * FmCF=0Hz (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/1 * Normal mode IDDHALT(6) HALT mode * FmCF=0Hz (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/1 * Power save mode IDDHALT(7) HALT mode * FmCF=0Hz (Oscillation stop) * FsX'tal=32.768kHz crystal oscillation * System clock: 32.768kHz * Internal RC oscillation stopped. * Divider: 1/2 * Power save mode Current consumption during HOLD mode Current consumption during Date/time X'tal HOLD mode IDDHOLD(2) Date/time clock HOLD mode * CF1=VDD or open (when using external clock) * FmX'tal=32.768kHz crystal oscillation * Internal RC oscillation stopped. * Divider: 1/1 * Normal mode IDDHOLD(3) Date/time clock HOLD mode * CF1=VDD or open (when using external clock) * FmX'tal=32.768kHz crystal oscillation * Internal RC oscillation stopped. * Divider: 1/1 * Power save mode 2.4 to 3.6 0.5 15 2.4 to 3.6 5.0 45 IDDHOLD(1) HOLD mode * CF1=VDD or open (when using external clock) 2.4 to 3.6 0.03 30 2.4 to 3.6 0.8 14 A 2.4 to 3.6 1.0 15 2.4 to 3.6 7.0 60 2.4 to 3.6 30 135 Conditions VDD[V] min Specification typ max unit
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
No.A0635-17/21
LC877816A
Main System Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Circuit parameters Frequency Manufacturer Type Oscillator C1 [pF] 4.00MHz Murata SMD Lead CSTCR4M00G53-R0 CSTLS4M00G53-B0 (15) (15) C2 [pF] (15) (15) Rd [] 1k 2.2k Operating supply voltage range[V] 2.4 to 3.6 2.4 to 3.6 Oscillation stabilizing time typ [ms] 0.2 0.2 max [ms] 0.6 0.6 Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 4)
Subsystem Clock Oscillation Circuit Characteristics
The characteristics in the table bellow is based on the following conditions: Use the standard evaluation board SANYO has provided. Use the peripheral parts with indicated value externally. The peripheral parts value is a recommended value of oscillator manufacturer Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Circuit parameters Frequency Manufacturer Oscillator C3 [pF] 32.768kHz Epson Toyocom MC-146 10 C4 [pF] 10 Rf [] Open Rd2 [] 0 Operating supply voltage range [V] 2.4 to 3.6 Oscillation stabilizing time typ [s] 1 max [s] 3 Notes
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the sub-clock oscillation or after releasing the HOLD mode. (See Fig. 4) Notes: Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2 Rd
XT1
XT2
Rf
Rd2
C1
CF
C2
C3 X'tal
C4
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0635-18/21
LC877816A
VDD Power Supply VDD limit 0V Reset time RES
Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution
Reset Time and Oscillation Stabilization
HOLD release signal
Without HOLD Release signal
HOLD release signal
Internal RC Resonator oscillation tmsCF CF1, CF2 tmsX'tal XT1, XT2
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Figure 4 Oscillation Stabilizing Time
No.A0635-19/21
LC877816A
VDD
RRES
Note: Select CRES and RRES value to assure that at least 200s reset time is generated after the VDD becomes higher than the minimum operating voltage.
RES CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (only SIO0)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Data RAM transfer period (only SIO0) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA
Figure 6 Serial Input/Output Wave Form
No.A0635-20/21
LC877816A
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of September, 2006. Specifications and information herein are subject to change without notice.
PS No.A0635-21/21

▲Up To Search▲

Price & Availability of LC877816A

	To Download LC877816A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .